FIG. 1 shows the block diagram of N-bit Successive Approximation Register Analog-Digital Converter (SAR ADC) comprising Track/Hold, Comparator, N-bit DAC and Binary Search Logic. The analog input voltage VIN is sampled and held by Track/Hold. The Binary Search Logic is initially set to midscale (100 . . . 00). This forces the DAC output VDAC to be VR/2, where VR is the reference voltage of ADC. The Comparator compares VIN and VDAC and determines the next operation based on the comparator result. If VIN is greater than VDAC, the comparator output is logic high and the most significant bit (MSB) of N-bit register remains at 1. Conversely, if VIN is less than VDAC, the comparator output is logic low and the MSB is cleared to logic 0. This binary-search process proceeds to the next MSB-1 bit test and completes the conversion once the least significant bit (LSB) output is obtained.
Capacitive DAC is often used to implement N-bit DAC owing to its inherent track/hold function. Therefore, both Track/Hold and DAC functions can be fulfilled using capacitive DAC. A capacitive DAC consists of an array of capacitors with binary or non-binary weighted values. It employs the principle of charge redistribution to generate an analog output voltage during the binary search process. FIG. 2 shows the exemplary implementation of 14-bit SARADC using 14-bit binary weighted capacitive DAC. During the sample phase, all the switches are connected to the input VIN. VIN voltage is effectively sampled and stored on the capacitors. As the first step of binary-search process begins, the bottom plate of MSB capacitor is connected to reference voltage VR. This drives the voltage of comparator inputs by an amount of 0.5VR. The comparator strobes and the comparator output value is stored. As the binary-search process continues, the next smaller capacitor is connected to VR. The conversion is complete once all the DAC capacitors are exercised. The relationship of VIN and SAR ADC digital output is described by the following equation:
            V      IN        =                  B        ⁢                                  ⁢        13        *                              V            ⁢                                                  ⁢            R                    2                    +              B        ⁢                                  ⁢        12        *                              V            ⁢                                                  ⁢            R                    4                    +      …      +              B        ⁢                                  ⁢        1        *                              V            ⁢                                                  ⁢            R                    8192                    +              B        ⁢                                  ⁢        0        *                              V            ⁢                                                  ⁢            R                    16384                                V      IN        ⁢                  ⁢    is    ⁢                  ⁢    the    ⁢                  ⁢    ADC    ⁢                  ⁢    input    ⁢                  ⁢    voltage              B      ⁡              [                  13          ⁢                      :                    ⁢          0                ]              ⁢                  ⁢    is    ⁢                  ⁢    ADC    ⁢                  ⁢    digital    ⁢                  ⁢    outputs        V    ⁢                  ⁢    R    ⁢                  ⁢    is    ⁢                  ⁢    ADC    ⁢                  ⁢    reference    ⁢                  ⁢    voltage  
When capacitive DAC is employed in the SAR ADC, the linearity of ADC is dictated by the capacitive DAC linearity. The mismatch between capacitors is the main source of non-linearity of capacitive DAC. For faster DAC settling, it is favorable to use smaller capacitor value. However, the mismatch gets worse as the capacitor dimension gets smaller.